Three-Dimensional Semiconductor Process Integration／International Project for Heterogeneous and Functional Integration
This research provides solutions to the limitation of high integration encountered in next-generation semiconductors. We are also mediating technology transfer and the acceleration of industrial implementation within the global supply chain through the WOW Alliance, fostering international collaboration. Driven by the development of the Internet-of-Things (IoT) economy, the global semiconductor market is expected to be worth over 400 trillion USD later than 2020. However, a key challenge in the widespread use of semiconductors is the low-cost scaling (miniaturization) for high integration due to the expensive lithography processes and facilities required during manufacturing. The development of systems with a non-flat spatial structure, called three-dimensional large-scale integrated technology, is expected to play an important part in solving this problem. For the first time, we have developed technologies for producing ultra-thin devices down to the micron-level using 300 mm wafers and interconnects without bumps between wafers.
In this project, we will characterize bonding materials to ensure high-reliability interconnects by evaluating the mechanical characteristics of the bonding materials in stack process and the electrical characteristics of vertical interconnects. Since circuit design (which can be thought of as the floor plan of the device) is derived from conventional planar scaling, it is possible to increase bandwidth fan-out and reduce power consumption in 3D devices through the use of high-density short interconnects without bumps in stack devices. Based on these technologies, it will become possible to manufacture ultra-small systems 1000 times smaller than current technologies comprising terabyte storage memory and microprocessor capabilities.