Simon Deleonibus

1981-1986 Thomson Semiconductors
1986-1996 Device Research Expert, CEA-LETI
1996-1998 Project Leader, CEA-LETI
1998-2008 Director, CEA-LETI
2008- Chief Scientist, CEA-LETI
2016 Professor (Specially Appointed), Institute of Innovative Research, Tokyo Institute of Technology

Nanoscale silicon devices

Laboratory for Future Interdisciplinary Research of Science and Technology(IIR, Tokyo Tech)

Research Hub Group:Materials and Devices international hub group

Research Highlights

  • Inventor in 1984 of “contact plug“ principle universally used by the microelectronics industry worldwide;
  • World record of smallest transistor in 1999 (Lg=20nm)

Selected Awards

  • 2006 IEEE Fellow
  • 2004 Chevalier de l’Ordre National du Mérite
  • 2011 Chevalier de l’Ordre des Palmes Académiques
  • 2005 Lauréat Grand Prix de l’Académie des Technologies

Selected Publications

  • Deleonibus S. , “Ultra Thin Films and Multigate Devices Architectures for future CMOS Scaling”, (Invited review paper) Science in China – Series F: Information Sciences , 54 ,5 (2011) , 990-1003, SPRINGER ; Science China Press
  • M. Rabarot, J. Widiez, S. Saada, J-P. Mazellier, J-C. Roussin, J. Dechamp, P. Bergonzo, F.Andrieu, O. Faynot, S. Deleonibus, L. Clavelier. , “Silicon-on-Diamond layer integration by wafer bonding technology”, Diamond and Related Materials, vol. 19, issue 7-9, pp. 796-805,2009,DOI: 10.1016/j.diamond.2010.01.049
  • M. Vinet, T. Poiroux, C. Licitra, J. Widiez, J. Bhandari, B. Previtali, C. Vizioz, D. Lafond, C. Arvet, P. Besson, L. Baud, Y. Morand, M. Rivoire, F. Nemouchi, V. Carron, and S. Deleonibus, “Self-Aligned Planar Double-Gate MOSFETs by Bonding for 22-nm Node, With Metal Gates, High-K Dielectrics, and Metallic Source/Drain”, IEEE Electron Device Letters, vol 30, n°7, pp 748-750, 2009
  • V. Barral, T. Poiroux, A. Bournel, J. Saint-Martin, D. Munteanu, J.L. Autran and S. Deleonibus, “Experimental investigation on the quasi-ballistic transport: Part I-Determination of a new backscattering coefficient extraction methodology” IEEE Trans. Electron Devices, 56, 408-419, 2009; Part II-Backscattering coefficient extraction and link with the mobility”, IEEE Trans. Electron Devices, 56, 420-430, 2009.
  • S. Poli, M. Pala, T. Poiroux, S. Deleonibus, and G. Baccarani, “Size dependence of surface-roughness-limited mobility in silicon-nanowire FETs,” IEEE Trans. Electron Devices, vol. 55, no. 11, pp. 2968–2976, Nov. 2008.