1984 Ph. D. University of Tokyo
1984-1994 Researcher, Fujitsu Labs. Ltd.
1994-1999 Senior Researcher, Fujitsu Labs. Ltd.
1999-2006 Director, LSI Materials Department, Fujitsu Labs.
2007-2013 Senior Vice President, Devices & Materials Labs., Fujitsu Labs. Ltd.
2013-2016 Senior Expert, Fujitsu Labs. Ltd.
2016- Specially Appointed Professor, FIRST, Tokyo Tech
Field of Specialization
Thin film process and characterization, Semiconductor materials, processes, and devices / LSI interconnects and reliability physics
Laboratory for Future Interdisciplinary Research of Science and Technology（IIR, Tokyo Tech）
Research Hub Group：Social Implementation
Characterized advanced materials and the interfacial structures for improving compound semiconductor device properties and LSI metallization reliabilities (1984-1999)
Developed advanced materials for improving metallization process, such as PVD-TiN and – Al, Ti and Co silicide, and electroplated Cu (1994-2000)
Directed and developed Cu/Low-k interconnect technologies from 90 nm to 45 nm node, and researched reliability-related failure mechanisms of Cu damascene interconnects (2000-2006)
Directed and developed Fan-out wafer level packaging with heterogeneous devices (2007-2013)
Developed characterization methodologies of materials and processes for 3D-stacked LSIs (2012-)
- Fellow, Japan Society of Applied Physics, 2014
- Advanced Metallization Conference Award 2014
- SSSJ Outstanding Contribution Award, The Surface Science Society of Japan, 2015
- Technical Award, The Japan Institute of Electronics packaging, 2015
- SSSJ Review Paper Award, The Surface Science Society of Japan, 2015
Y. Mizushima, T. Nakamura et al. (2017), Behavior of copper contamination on backside damage for ultra-thin silicon three dimensional stacking structure, Microelectron. Eng. 167 23.
Aki Dote, Tomoji Nakamura et al.(2016), Analyzing and modeling methods for warpages of thin and large dies with redistribution layer, Jpn. J. Appl. Phys. 55, 06JC03.
Tadahiro Imada, Tomoji Nakamura et al. (2015), Systematic investigation of silylation materials for recovery use of low- k material plasma damage, Jpn. J. Appl. Phys., 54, 071502.
LSI Interconnect Technology and Surface Science, Journal of SSSJ, 35, 236
T. Nakamura, et al. (2013), Influence of wafer thinning process on backside damage in 3D integration, IEEE International 3D Systems Integration Conference (3DIC).
T. Nakamura (2013）Surface modification technologies: An overview, Oyo Buturi, 82, 376
T. Nakamura, T. Suzuki (2009）Reliability of LSI multilayer interconnects, Oyo Buturi, 78, 873